Innovative DRAM Solutions

Heterogeneous integration certainly offers a solution for performance scaling that was regarded as the momentum to continue the development of the semiconductor industry. Etron Technology (TPEx: 5351.TW) – a leading semiconductor provider with both design capabilities of memory and logic – has successively develop several innovative memory solutions, which are widely used in various emerging areas, including AI, 5G, cloud computing and automotive, etc.

AI (Artificial Intelligence) has dramatically increased the demand at the IoT edge. In response to this demand, Etron’s world’s first DRAM in Fan-In Wafer Level Package, RPC DRAM^®, supports high bandwidth and reduced form-factor. With the advantages of cost performance and low power consumption of RPC DRAM, the innovative DRAM is the ideal memory for use in many wearable devices and miniature AI cameras on IoT devices.

In addition to emerging memory development, Etron continues to strengthen its specialty DRAM development, which recently developed LRTDRAM^TM products through DRAM circuit design. It can significantly extend the retention time of DRAM under the JEDEC standard. This is best for the high-temperature applications, such as automotive and KGD. the overall DRAM performance can be significantly improved under the condition of high temperature.

In addition, to meet the needs of AI-Edge devices, Etron also invents high-bandwidth and Long-Retention DRAM and is engaged in in-depth research and development of future products. We are using different types of HBM to challenge the bandwidth requirements of GDDR5 grades from 10GB/s to 400GB/s, meet the increasing computing and data throughput of AI SoCs, and provide a one-stop solution that combines controller and DRAM for customer needs.

In the era of Heterogeneous Integration, we continue to work on the JEDEC niche DRAM die. We are developing the ability to reduce the operating voltage of DRAM circuits from 1.5 volts to 0.7 volts and meet the retention time requirements defined by the JEDEC standard. This move can significantly reduce the power consumption of standard DRAM and flip the circuit design so that the scaling of DRAM continues to extend into a new era.