A Second-Path Moore’s Law Scaling (2PMLS) Below 10nm to Optimize PPACT- Part I: Inventions on Outside-Gate Structures for Fin/GAA-Transistors and 6T SRAM Cells with Modeling Results

《A Second-Path Moore’s Law Scaling (2PMLS) Below 10nm to Optimize PPACT – Part I》 focuses on innovative approaches for sub-10nm nodes, with in-depth exploration of outside-gate structures for FinFET and GAA transistors, as well as design optimizations for 6T SRAM cells.

JEDEC STANDARD DRAM

DDR/ DDR2/ DDR3/ DDR4
LPDDR2/ LPDDR4/ SDR

KGDM™
Known Good Die Memory

A Pioneer and Leader in KGD Memory

• Enable the Integration of Memory and System-Chip in One Package

RPC DRAM^®
Low Pin Count DRAM

World′s 1st DRAM in Wafer Level Chip Size Package (WLCSP)

• The Smallest and Least Expensive Package Option

Monolithic and Heterogeneous Integration (MHI™)

• Optimizing MHI of Si & Non-Si Materials/Devices
• Creating Self-Smart MicroSystems