Empowering the Next Era of AI Memory, Edge Intelligence & Privacy Computing

Highlights on Display

• MemorAiLink® AI Memory Platform – One-stop memory + IP + packaging integration for superior AI SoC efficiency
• RPC® inside G120 Subsystem– Hsinchu Science Park award-winning AI edge solution featuring compact, low-power RPC DRAM®
• eYs3D Physical AI– Stereo vision & edge computing platforms enabling autonomy in robots, drones & smart infrastructure
• DeCloak Privacy-Intelligent AI – Real-time de-identification with CES Innovation Awards honoree technologies
• eEver USB PD3.2 Solutions – Certified USB Type-C power delivery controllers for next-generation devices

📍 Meet Etron at CES 2026, booth 14841(LVCC)

📅 Las Vegas • Jan. 6–9, 2026

We look forward to connecting with you.

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ESWEEK 2025 – Embedded System Week – Dr Nicky Lu’s Slide Deck

Challenges in the Symbiosis between Semiconductors and AI: Optimizing Cost-Performance-Power through Second-Path Moore’s Law Scaling, Especially for Edge-AI Embedded Systems

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A Second-Path Moore’s Law Scaling (2PMLS) Below 10nm to Optimize PPACT- Part I: Inventions on Outside-Gate Structures for Fin/GAA-Transistors and 6T SRAM Cells with Modeling Results

《A Second-Path Moore’s Law Scaling (2PMLS) Below 10nm to Optimize PPACT – Part I》。本篇聚焦于10奈米以下节点的创新途径，深入探讨FinFET与GAA晶体管结构的外闸技术（Outside-Gate Structures），以及6T SRAM单元的设计优化。

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Challenges to Symbiotic Growth of Semiconductor & AI Industries: A 2nd-Path Moore’s Law Scaling for Deep, Broad, and Exponential Intelligence Economics

DRC是一个透过动手设计、团队合作与问题解决来促进创新的平台。它鼓励跨部门协作与实作学习，推动具实质价值的研发成果。

JEDEC标准型DRAM

DDR/ DDR2/ DDR3/ DDR4
LPDDR2/ LPDDR4/ SDR

KGDM™
良品裸晶存储器 (Known Good Die Memory)

KGDM™ 良品裸晶记忆体之先驱领导者

• 驱动存储器与系统芯片整合为单一封装

RPC DRAM^®
低接脚数 DRAM (Low Pin Count DRAM)

全球第一颗采用晶圆级晶粒封装 (WLCSP) 之DRAM

• 提供兼具小型化与成本效益的封装选项

同体异质整合加乘 (Monolithic and Heterogeneous Integration, MHI™)

• 将矽和非矽之材料与元件的同体异质整合最佳化
• 创造由奈米硅核心与AI技术支援的Self-Smart微系统